[Techtalk] Re: Loop/wildcard-like syntax for GNU make?

[Conor Daly]

On Fri, Apr 20, 2007 at 12:58:31AM +0200 or so it is rumoured hereabouts, 
Wim De Smet thought:
> On 4/20/07, Conor Daly <conor.daly-linuxchix at cod.homelinux.org> wrote:
> >On Thu, Apr 19, 2007 at 06:43:17PM +0200 or so it is rumoured hereabouts,
> >Michelle Konzack thought:
> >> Am 2007-04-18 09:28:51, schrieb Conor Daly:
> >> > This works for a straight cp and should work with convert also:
> >> >
> >> > all:
> >> >     for FILE in *.png; do \
> >> >             cp -f $$FILE $$(basename "$$FILE" png)jpg; \
> >> >     done;
> >>
> >> Please read the manual to gnu make why you should avoid shell loops.
> >
> >I read the manual far enough to figure out _how_ to do shell loops.  Now I
> >have to go and read why not?!!!  Arrgh!!
> >
> 
> Heh, I think the point is that if you use a loop to do this, make has
> no idea whether any of the files need updating, so every time you do
> this all the files will be updated, and not just the ones that need
> it.

Ah!  So, in my case, I'm using the shell loop only in my uninstall target
to
remove installed manpages.  I think in that instance it's ok to use.  My
shell loop looks like:

uninstall:
        su dba -c 'rm -f $(LOCAL_LIB_DIR)$(Libname); \
                rm -f $(LOCAL_LIB_DIR)$(LibSOname); \
                rm -f $(LOCAL_INCLUDE_DIR)qc/libmetqc.h; \
                rm -f $(LOCAL_INCLUDE_DIR)qc/sql.h; \
                rmdir $(LOCAL_INCLUDE_DIR)qc; \
                for FILE in ../man3/*.3; do \
                        rm -f $(MANDIR)/man3/$$(basename "$$FILE"); \
                done; '
 
> There, saved you 10 minutes at least. :-)

You're a darling...

Started reading anyway and I did discover something really cool...

 ]$ info make

Implicit Rules:  Use implicit rules to treat many files alike, based on
	their file names.

There is already an implicit rule for making .o files from .c which uses:

	$(CC) $(CFLAGS) -c -o $@ $<

which means:  "for any .c file, make a .o file by doing that command." 
$@ is the output file (the .o) and $< is the input file (the .c)  I can
just add a .c file to my build and it will automatically compile...  Cool!

I then have to define an implicit rule for my embedded sql files something
like this:

%.c : %.sc
	esqlc $<

and make will automatically preprocess any .sc files for me.

Conor (trotting off to rewrite _all_ his Makefiles...)
-- 
Conor Daly <conor.daly at cod.homelinux.org>
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